Shallow trench isolation (STI), also known as Box Isolation Technique, is an integrated circuit feature which prevents electrical current leakage between adjacent semiconductor device components and prevents ion penetration between two different doped regions.
But a common STI structure of a traditional metal-oxide-semiconductor field-effect transistor (MOSFET) may have a lower level than that of adjacent semiconductor device components, and that will cause a weaker ability in avoiding ion penetration issues and leakage current issues.
In view of the aforementioned reasons, there is a need to provide a new MOSFET structure to improve efficiency in preventing ion penetration issues and leakage current issues.